Design of an automated rail transit system controller: Malaysia perspective - Ibrahimy, Muhammad Ibn; Hasan, Muhammad Asfarul; Ullah, Mohammad Habib (INSI Publications, 2009)
The objective of this project is to model an automatic rail transit controller using VHDL (VHSIC hardware description language) that can control the train in one particular station. The controller can control the power to the tracks, and the direction of the trains. This is to make sure that only one train at a station at a particular time and can therefore be avoided the collision of trains. The process of testing has been done during modeling the process in order to make sure that the design is working successfully. Altera Quartus II Web Edition software tool is used to synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. The result in simulation and implementation in the FPGA (Field Programmable Gate Array) shows that the designed model is working satisfactory.