APA (7th ed.) Citation

Ibrahimy, M. I., Ahsan, M. R., & Bambang Soeroso, I. (2012). Hardware modeling of binary coded decimal adder in FPGA. World Scientific and Engineering Academy and Society.

Chicago Style (17th ed.) Citation

Ibrahimy, Muhammad Ibn, Md. Rezwanul Ahsan, and Iksannurazmi Bambang Soeroso. Hardware Modeling of Binary Coded Decimal Adder in FPGA. World Scientific and Engineering Academy and Society, 2012.

MLA (8th ed.) Citation

Ibrahimy, Muhammad Ibn, et al. Hardware Modeling of Binary Coded Decimal Adder in FPGA. World Scientific and Engineering Academy and Society, 2012.