Single core hardware module to implement encryption in TECB mode

The growth of the Internet as a vehicle for secure communication has resulted in Data Encryption Standard (DES) no longer capable of providing high-level security for data protection. Triple Data Encryption Standard (3DES) is a symmetric block cipher with 192 bits key proposed to further enhance DES...

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Main Authors:	Reaz, Mamun Bin Ibne, Ibrahimy, Muhammad Ibn, Mohd-Yasin, Faisal, C., S. Wei, Kamada, Masaru
Format:	Article
Language:	English
Published:	"Society for Microelectronics, Electric Components and Materials " 2007
Subjects:	T Technology (General)
Online Access:	http://irep.iium.edu.my/29534/ http://irep.iium.edu.my/29534/ http://irep.iium.edu.my/29534/1/MIDEM_37%282007%293p165.pdf

id	iium-29534
recordtype	eprints
spelling	iium-295342015-08-12T04:01:22Z http://irep.iium.edu.my/29534/ Single core hardware module to implement encryption in TECB mode Reaz, Mamun Bin Ibne Ibrahimy, Muhammad Ibn Mohd-Yasin, Faisal C., S. Wei Kamada, Masaru T Technology (General) The growth of the Internet as a vehicle for secure communication has resulted in Data Encryption Standard (DES) no longer capable of providing high-level security for data protection. Triple Data Encryption Standard (3DES) is a symmetric block cipher with 192 bits key proposed to further enhance DES. Many applications crave for the speed of a hardware encryption implementation while trying to preserve the flexibility and low cost of a software implementation. This project used single core module to implement encryption in Triple DES Electronic Code Book (TECB) mode, which was modeled using hardware description language VHDL. The architecture was mapped in Altera EPF10K100EFC484-1 and EP20K200EFC672-1X for performance investigations and resulted in achieving encryption rate of 102.56 Mbps, area utilization of 2111 logic cells (25%) and a higher maximum operating frequency of 78.59 MHz by implementing on the larger FPGA device EP20K200EFC672-1X. It also suggested that 3DES hardware was 2.4 times faster than its software counterpart. "Society for Microelectronics, Electric Components and Materials " 2007-09 Article PeerReviewed application/pdf en http://irep.iium.edu.my/29534/1/MIDEM_37%282007%293p165.pdf Reaz, Mamun Bin Ibne and Ibrahimy, Muhammad Ibn and Mohd-Yasin, Faisal and C., S. Wei and Kamada, Masaru (2007) Single core hardware module to implement encryption in TECB mode. Informacije MIDEM: Journal of Microelectronics, Electronic Components and Materials, 37 (3). pp. 165-171. ISSN 0352-9045 http://www.midem-drustvo.si/journal.htm
repository_type	Digital Repository
institution_category	Local University
institution	International Islamic University Malaysia
building	IIUM Repository
collection	Online Access
language	English
topic	T Technology (General)
spellingShingle	T Technology (General) Reaz, Mamun Bin Ibne Ibrahimy, Muhammad Ibn Mohd-Yasin, Faisal C., S. Wei Kamada, Masaru Single core hardware module to implement encryption in TECB mode
description	The growth of the Internet as a vehicle for secure communication has resulted in Data Encryption Standard (DES) no longer capable of providing high-level security for data protection. Triple Data Encryption Standard (3DES) is a symmetric block cipher with 192 bits key proposed to further enhance DES. Many applications crave for the speed of a hardware encryption implementation while trying to preserve the flexibility and low cost of a software implementation. This project used single core module to implement encryption in Triple DES Electronic Code Book (TECB) mode, which was modeled using hardware description language VHDL. The architecture was mapped in Altera EPF10K100EFC484-1 and EP20K200EFC672-1X for performance investigations and resulted in achieving encryption rate of 102.56 Mbps, area utilization of 2111 logic cells (25%) and a higher maximum operating frequency of 78.59 MHz by implementing on the larger FPGA device EP20K200EFC672-1X. It also suggested that 3DES hardware was 2.4 times faster than its software counterpart.
format	Article
author	Reaz, Mamun Bin Ibne Ibrahimy, Muhammad Ibn Mohd-Yasin, Faisal C., S. Wei Kamada, Masaru
author_facet	Reaz, Mamun Bin Ibne Ibrahimy, Muhammad Ibn Mohd-Yasin, Faisal C., S. Wei Kamada, Masaru
author_sort	Reaz, Mamun Bin Ibne
title	Single core hardware module to implement encryption in TECB mode
title_short	Single core hardware module to implement encryption in TECB mode
title_full	Single core hardware module to implement encryption in TECB mode
title_fullStr	Single core hardware module to implement encryption in TECB mode
title_full_unstemmed	Single core hardware module to implement encryption in TECB mode
title_sort	single core hardware module to implement encryption in tecb mode
publisher	"Society for Microelectronics, Electric Components and Materials "
publishDate	2007
url	http://irep.iium.edu.my/29534/ http://irep.iium.edu.my/29534/ http://irep.iium.edu.my/29534/1/MIDEM_37%282007%293p165.pdf
first_indexed	2023-09-18T20:43:22Z
last_indexed	2023-09-18T20:43:22Z
_version_	1777409513064759296

Single core hardware module to implement encryption in TECB mode

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