Network-on-chip implementation of hierarchical torus network
The interconnection network plays an important role in the performance and energy consumption of a Network-on-Chip (NoC) system. In this paper, we implement the NoC implementation of hierarchical torus network. The Hierarchical Torus Network (HTN) is a hierarchical interconnection network consisti...
| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Language: | English English |
| Published: |
2013
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| Subjects: | |
| Online Access: | http://irep.iium.edu.my/31743/ http://irep.iium.edu.my/31743/1/ICSECS_2013_HTN_24_pub.pdf http://irep.iium.edu.my/31743/4/ICSECS_2013.jpg |
| Summary: | The interconnection network plays an important role in the
performance and energy consumption of a Network-on-Chip (NoC) system. In this paper, we implement the NoC implementation of hierarchical torus network. The Hierarchical Torus Network (HTN) is a hierarchical
interconnection network consisting of multiple BM that is hierarchically interconnected for higher-level networks. The number of layers needed for routing the links in HTN level-2 is shown to be bounded at 8, which is feasible to be implemented with current and future VLSI technologies.
With the innovative hierarchical structure, HTN possesses the following features: hierarchical structure, smaller diameter and average distance, embedded mesh/torus topology, a constant node degree of 8. These features make HTN a promising solution for the interconnection network of NoC designs satisfying the requirements for scalability, energy efficiency, customizable, and fault-tolerance. |
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