Network-on-chip implementation of hierarchical torus network

Network-on-chip implementation of hierarchical torus network

The interconnection network plays an important role in the performance and energy consumption of a Network-on-Chip (NoC) system. In this paper, we implement the NoC implementation of hierarchical torus network. The Hierarchical Torus Network (HTN) is a hierarchical interconnection network consisti...

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Main Authors: Rahman, M.M. Hafizur, Ray, Sajib, Md. , Rabiul Awal
Format: Conference or Workshop Item
Language:English
English
Published: 2013
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://irep.iium.edu.my/31743/
http://irep.iium.edu.my/31743/1/ICSECS_2013_HTN_24_pub.pdf
http://irep.iium.edu.my/31743/4/ICSECS_2013.jpg
id iium-31743
recordtype eprints
spelling iium-317432013-09-24T07:40:37Z http://irep.iium.edu.my/31743/ Network-on-chip implementation of hierarchical torus network Rahman, M.M. Hafizur Ray, Sajib Md. , Rabiul Awal TK Electrical engineering. Electronics Nuclear engineering The interconnection network plays an important role in the performance and energy consumption of a Network-on-Chip (NoC) system. In this paper, we implement the NoC implementation of hierarchical torus network. The Hierarchical Torus Network (HTN) is a hierarchical interconnection network consisting of multiple BM that is hierarchically interconnected for higher-level networks. The number of layers needed for routing the links in HTN level-2 is shown to be bounded at 8, which is feasible to be implemented with current and future VLSI technologies. With the innovative hierarchical structure, HTN possesses the following features: hierarchical structure, smaller diameter and average distance, embedded mesh/torus topology, a constant node degree of 8. These features make HTN a promising solution for the interconnection network of NoC designs satisfying the requirements for scalability, energy efficiency, customizable, and fault-tolerance. 2013 Conference or Workshop Item PeerReviewed application/pdf en http://irep.iium.edu.my/31743/1/ICSECS_2013_HTN_24_pub.pdf application/pdf en http://irep.iium.edu.my/31743/4/ICSECS_2013.jpg Rahman, M.M. Hafizur and Ray, Sajib and Md. , Rabiul Awal (2013) Network-on-chip implementation of hierarchical torus network. In: 3rd International Conference on Software Engineering and Computer Systems (ICSECS - 2013), 20 - 22 August 2013, Kuantan, Pahang.
repository_type Digital Repository
institution_category Local University
institution International Islamic University Malaysia
building IIUM Repository
collection Online Access
language English
English
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Rahman, M.M. Hafizur
Ray, Sajib
Md. , Rabiul Awal
Network-on-chip implementation of hierarchical torus network
description The interconnection network plays an important role in the performance and energy consumption of a Network-on-Chip (NoC) system. In this paper, we implement the NoC implementation of hierarchical torus network. The Hierarchical Torus Network (HTN) is a hierarchical interconnection network consisting of multiple BM that is hierarchically interconnected for higher-level networks. The number of layers needed for routing the links in HTN level-2 is shown to be bounded at 8, which is feasible to be implemented with current and future VLSI technologies. With the innovative hierarchical structure, HTN possesses the following features: hierarchical structure, smaller diameter and average distance, embedded mesh/torus topology, a constant node degree of 8. These features make HTN a promising solution for the interconnection network of NoC designs satisfying the requirements for scalability, energy efficiency, customizable, and fault-tolerance.
format Conference or Workshop Item
author Rahman, M.M. Hafizur
Ray, Sajib
Md. , Rabiul Awal
author_facet Rahman, M.M. Hafizur
Ray, Sajib
Md. , Rabiul Awal
author_sort Rahman, M.M. Hafizur
title Network-on-chip implementation of hierarchical torus network
title_short Network-on-chip implementation of hierarchical torus network
title_full Network-on-chip implementation of hierarchical torus network
title_fullStr Network-on-chip implementation of hierarchical torus network
title_full_unstemmed Network-on-chip implementation of hierarchical torus network
title_sort network-on-chip implementation of hierarchical torus network
publishDate 2013
url http://irep.iium.edu.my/31743/
http://irep.iium.edu.my/31743/1/ICSECS_2013_HTN_24_pub.pdf
http://irep.iium.edu.my/31743/4/ICSECS_2013.jpg
first_indexed 2023-09-18T20:45:53Z
last_indexed 2023-09-18T20:45:53Z
_version_ 1777409671480475648

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