VHDL modeling and simulation of the back-propagation algorithm and its mapping to the RM
The Reconfigurable Machine (RM) is a parallel architecture that is built using Xilinx's 4005 Field Programmable Gate Array (FPGA) and associated fast SRAMs. In this study, VHDL modeling and simulation of a fully connected there-layer Back-Propagation (BP) is attempted with a view towards its ma...
| Main Authors: | , , |
|---|---|
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
1993
|
| Subjects: | |
| Online Access: | http://irep.iium.edu.my/38341/ http://irep.iium.edu.my/38341/ http://irep.iium.edu.my/38341/1/VHDL_modeling_and_simulation_of_the_back-propagation_algorithm_and_its_mapping_to_the_RM.pdf |
| Summary: | The Reconfigurable Machine (RM) is a parallel architecture that is built using Xilinx's 4005 Field Programmable Gate Array (FPGA) and associated fast SRAMs. In this study, VHDL modeling and simulation of a fully connected there-layer Back-Propagation (BP) is attempted with a view towards its mapping to a reconfigurable . parallel architecture. The mapping encompasses both the forward and backward passes. A
bottom-up approach is used which starts from the configuration of processing elements to achieve effective
computation of floating-point sum-of-products. The FPGAs perform the floating-point multiplication, addition and function evaluation, while the local SRAMs are used for storing U0 data for RM. |
|---|