Design of a high-speed, reconfigurable digital rank order filter

A new architecture to realize a modular, high speed, reconfigurable, digital Rank Order Filter (ROF) is presented in this paper. A bit-level algorithm by Kar and Pradhan has been modified in this work to implement the proposed ROF. Using the proposed digital rank selection circuit it is possible to...

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Main Authors:	Toscano, George John, Saha, Pran Kanai, Alam, A. H. M. Zahirul
Format:	Article
Language:	English
Published:	IIUM Press 2009
Subjects:	TK7885 Computer engineering
Online Access:	http://irep.iium.edu.my/4496/ http://irep.iium.edu.my/4496/ http://irep.iium.edu.my/4496/1/Design_of_a_high-speed%2C_reconfigurable_digital_rank_order_filter.pdf

id	iium-4496
recordtype	eprints
spelling	iium-44962012-12-14T00:56:10Z http://irep.iium.edu.my/4496/ Design of a high-speed, reconfigurable digital rank order filter Toscano, George John Saha, Pran Kanai Alam, A. H. M. Zahirul TK7885 Computer engineering A new architecture to realize a modular, high speed, reconfigurable, digital Rank Order Filter (ROF) is presented in this paper. A bit-level algorithm by Kar and Pradhan has been modified in this work to implement the proposed ROF. Using the proposed digital rank selection circuit it is possible to find the element of a certain rank in a given sequence of N elements in each window in M steps, where M is the number of bits used in binary representation for the elements of the sequence. The size of the proposed ROF increases only linearly with the number of samples in each window to be ranked. The proposed ROF is also modular in nature, which means function of each part of the ROF is well defined and so the circuit can be easily expandable for larger window size. The proposed ROF has been implemented in FGPA and post-fit simulation results are presented in this paper. HSPICE simulation of the proposed ROF is also done for 0.18µm CMOS process. IIUM Press 2009 Article PeerReviewed application/pdf en http://irep.iium.edu.my/4496/1/Design_of_a_high-speed%2C_reconfigurable_digital_rank_order_filter.pdf Toscano, George John and Saha, Pran Kanai and Alam, A. H. M. Zahirul (2009) Design of a high-speed, reconfigurable digital rank order filter. IIUM Engineering Journal, 10 (1). pp. 19-30. ISSN 1511-788X http://www.iium.edu.my/ejournal/home2010/index.php/iiumej/article/view/102
repository_type	Digital Repository
institution_category	Local University
institution	International Islamic University Malaysia
building	IIUM Repository
collection	Online Access
language	English
topic	TK7885 Computer engineering
spellingShingle	TK7885 Computer engineering Toscano, George John Saha, Pran Kanai Alam, A. H. M. Zahirul Design of a high-speed, reconfigurable digital rank order filter
description	A new architecture to realize a modular, high speed, reconfigurable, digital Rank Order Filter (ROF) is presented in this paper. A bit-level algorithm by Kar and Pradhan has been modified in this work to implement the proposed ROF. Using the proposed digital rank selection circuit it is possible to find the element of a certain rank in a given sequence of N elements in each window in M steps, where M is the number of bits used in binary representation for the elements of the sequence. The size of the proposed ROF increases only linearly with the number of samples in each window to be ranked. The proposed ROF is also modular in nature, which means function of each part of the ROF is well defined and so the circuit can be easily expandable for larger window size. The proposed ROF has been implemented in FGPA and post-fit simulation results are presented in this paper. HSPICE simulation of the proposed ROF is also done for 0.18µm CMOS process.
format	Article
author	Toscano, George John Saha, Pran Kanai Alam, A. H. M. Zahirul
author_facet	Toscano, George John Saha, Pran Kanai Alam, A. H. M. Zahirul
author_sort	Toscano, George John
title	Design of a high-speed, reconfigurable digital rank order filter
title_short	Design of a high-speed, reconfigurable digital rank order filter
title_full	Design of a high-speed, reconfigurable digital rank order filter
title_fullStr	Design of a high-speed, reconfigurable digital rank order filter
title_full_unstemmed	Design of a high-speed, reconfigurable digital rank order filter
title_sort	design of a high-speed, reconfigurable digital rank order filter
publisher	IIUM Press
publishDate	2009
url	http://irep.iium.edu.my/4496/ http://irep.iium.edu.my/4496/ http://irep.iium.edu.my/4496/1/Design_of_a_high-speed%2C_reconfigurable_digital_rank_order_filter.pdf
first_indexed	2023-09-18T20:12:44Z
last_indexed	2023-09-18T20:12:44Z
_version_	1777407586179481600

Design of a high-speed, reconfigurable digital rank order filter

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