A high radix hierarchical interconnection network for network-on-chip
Architecture of the interconnection network has a great influence on the speed of the multi-core processor design. The main aims of any new architecture are to avoid the latency, and to decrease the cost. In this paper, we proposed new hierarchical interconnection network, in order to build fast par...
| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Language: | English English |
| Published: |
Springer International Publishing
2016
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| Subjects: | |
| Online Access: | http://irep.iium.edu.my/51096/ http://irep.iium.edu.my/51096/ http://irep.iium.edu.my/51096/ http://irep.iium.edu.my/51096/1/51096_A_High_Radix_Hierarchical_Interconnection.pdf http://irep.iium.edu.my/51096/2/51096_A_high_radix_hierarchical_interconnection_SCOPUS.pdf |
| Summary: | Architecture of the interconnection network has a great influence on the speed of the multi-core processor design. The main aims of any new architecture are to avoid the latency, and to decrease the cost. In this paper, we proposed new hierarchical interconnection network, in order to build fast parallel computing system. We have evaluated the static network performance of the proposed network
such as: node degree, diameter, cost, arc connectivity, bisection width, and wiring complexity. The proposed topology achieved low cost and small diameter comparing
to 2D-mesh, and 2D-torus topologies. As well as, it gives good results in the other static parameters. Hence, the proposed network is good solution to improve the performance, and decrease the cost of the interconnection networks for the future generation parallel computing systems. |
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