A high radix hierarchical interconnection network for network-on-chip

Architecture of the interconnection network has a great influence on the speed of the multi-core processor design. The main aims of any new architecture are to avoid the latency, and to decrease the cost. In this paper, we proposed new hierarchical interconnection network, in order to build fast par...

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Main Authors: N.M. Ali, Mohammed, Rahman, M.M. Hafizur, Mohd. Nor, Rizal, Tengku Sembok, Tengku Mohd
Format: Conference or Workshop Item
Language:English
English
Published: Springer International Publishing 2016
Subjects:
Online Access:http://irep.iium.edu.my/51096/
http://irep.iium.edu.my/51096/
http://irep.iium.edu.my/51096/
http://irep.iium.edu.my/51096/1/51096_A_High_Radix_Hierarchical_Interconnection.pdf
http://irep.iium.edu.my/51096/2/51096_A_high_radix_hierarchical_interconnection_SCOPUS.pdf
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recordtype eprints
spelling iium-510962017-01-06T07:14:50Z http://irep.iium.edu.my/51096/ A high radix hierarchical interconnection network for network-on-chip N.M. Ali, Mohammed Rahman, M.M. Hafizur Mohd. Nor, Rizal Tengku Sembok, Tengku Mohd TK Electrical engineering. Electronics Nuclear engineering TK7800 Electronics. Computer engineering. Computer hardware. Photoelectronic devices Architecture of the interconnection network has a great influence on the speed of the multi-core processor design. The main aims of any new architecture are to avoid the latency, and to decrease the cost. In this paper, we proposed new hierarchical interconnection network, in order to build fast parallel computing system. We have evaluated the static network performance of the proposed network such as: node degree, diameter, cost, arc connectivity, bisection width, and wiring complexity. The proposed topology achieved low cost and small diameter comparing to 2D-mesh, and 2D-torus topologies. As well as, it gives good results in the other static parameters. Hence, the proposed network is good solution to improve the performance, and decrease the cost of the interconnection networks for the future generation parallel computing systems. Springer International Publishing 2016-06 Conference or Workshop Item PeerReviewed application/pdf en http://irep.iium.edu.my/51096/1/51096_A_High_Radix_Hierarchical_Interconnection.pdf application/pdf en http://irep.iium.edu.my/51096/2/51096_A_high_radix_hierarchical_interconnection_SCOPUS.pdf N.M. Ali, Mohammed and Rahman, M.M. Hafizur and Mohd. Nor, Rizal and Tengku Sembok, Tengku Mohd (2016) A high radix hierarchical interconnection network for network-on-chip. In: 12th International Conference on Computing and Information Technology (IC2IT), 7th-8th July 2016, Khon Kaen, Thailand. http://link.springer.com/chapter/10.1007%2F978-3-319-40415-8_24 10.1007/978-3-319-40415-8_24
repository_type Digital Repository
institution_category Local University
institution International Islamic University Malaysia
building IIUM Repository
collection Online Access
language English
English
topic TK Electrical engineering. Electronics Nuclear engineering
TK7800 Electronics. Computer engineering. Computer hardware. Photoelectronic devices
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
TK7800 Electronics. Computer engineering. Computer hardware. Photoelectronic devices
N.M. Ali, Mohammed
Rahman, M.M. Hafizur
Mohd. Nor, Rizal
Tengku Sembok, Tengku Mohd
A high radix hierarchical interconnection network for network-on-chip
description Architecture of the interconnection network has a great influence on the speed of the multi-core processor design. The main aims of any new architecture are to avoid the latency, and to decrease the cost. In this paper, we proposed new hierarchical interconnection network, in order to build fast parallel computing system. We have evaluated the static network performance of the proposed network such as: node degree, diameter, cost, arc connectivity, bisection width, and wiring complexity. The proposed topology achieved low cost and small diameter comparing to 2D-mesh, and 2D-torus topologies. As well as, it gives good results in the other static parameters. Hence, the proposed network is good solution to improve the performance, and decrease the cost of the interconnection networks for the future generation parallel computing systems.
format Conference or Workshop Item
author N.M. Ali, Mohammed
Rahman, M.M. Hafizur
Mohd. Nor, Rizal
Tengku Sembok, Tengku Mohd
author_facet N.M. Ali, Mohammed
Rahman, M.M. Hafizur
Mohd. Nor, Rizal
Tengku Sembok, Tengku Mohd
author_sort N.M. Ali, Mohammed
title A high radix hierarchical interconnection network for network-on-chip
title_short A high radix hierarchical interconnection network for network-on-chip
title_full A high radix hierarchical interconnection network for network-on-chip
title_fullStr A high radix hierarchical interconnection network for network-on-chip
title_full_unstemmed A high radix hierarchical interconnection network for network-on-chip
title_sort high radix hierarchical interconnection network for network-on-chip
publisher Springer International Publishing
publishDate 2016
url http://irep.iium.edu.my/51096/
http://irep.iium.edu.my/51096/
http://irep.iium.edu.my/51096/
http://irep.iium.edu.my/51096/1/51096_A_High_Radix_Hierarchical_Interconnection.pdf
http://irep.iium.edu.my/51096/2/51096_A_high_radix_hierarchical_interconnection_SCOPUS.pdf
first_indexed 2023-09-18T21:12:18Z
last_indexed 2023-09-18T21:12:18Z
_version_ 1777411333363335168