Design and implementation of a five stage pipelining architecture simulator for RiSC-16 instruction set
In modern computing, multitasking is the most favorable aspect. An un-pipelined instruction cycle (fetch-execute cycle) CPU processes instructions one after another increasing duration at lesser speed in completing tasks. With pipelined computer architecture, unprecedented improvement in size and...
| Main Authors: | , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Indian Society of Education and Environment
2017
|
| Subjects: | |
| Online Access: | http://irep.iium.edu.my/56118/ http://irep.iium.edu.my/56118/ http://irep.iium.edu.my/56118/ http://irep.iium.edu.my/56118/1/Design%20of%20Pipeline%20published.pdf |
| Summary: | In modern computing, multitasking is the most favorable aspect. An un-pipelined instruction cycle (fetch-execute cycle)
CPU processes instructions one after another increasing duration at lesser speed in completing tasks. With pipelined
computer architecture, unprecedented improvement in size and speed are achievable. This work investigates the possibility
of a better improvement to computer architecture through understanding the inner workings of instruction pipelining
in operating system. A design of a 5 stage pipelined architecture simulator for RiSC-16 processors using Visual Basic
programming has been achieved contrary to the common available four stage simulators. The simulator also future two
most common pipeline instruction hazards generally missing in most available simulators. Thus, the designed simulator
becomes an appropriate tool for understanding the concept of pipelining on a step-by-step visualization based instruction cycle
processors hence facilitating a more efficient design in computer architecture. The simulator has been evaluated
based on its closeness to real-time pipelined computer architecture and through execution of all 8 basic RiSC-16 instruction
set with data dependency and control hazard. |
|---|