Hardware prototyping of an efficient encryption engine

An approach to develop the FPGA of a flexible key RSA encryption engine that can be used as a standard device in the secured communication system is presented. The VHDL modeling of this RSA encryption engine has the unique characteristics of supporting multiple key sizes, thus can easily be fit...

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Main Authors:	Ibrahimy, Muhammad Ibn, Reaz, Mamun Bin Ibne, Asaduzzaman, Md., Chowdhury, Md. Sazzad Hossien
Format:	Article
Language:	English
Published:	World Academy of Science Engineering and Technology 2010
Subjects:	TK7885 Computer engineering
Online Access:	http://irep.iium.edu.my/5971/ http://irep.iium.edu.my/5971/ http://irep.iium.edu.my/5971/1/Hardware_Prototyping_2010.pdf

id	iium-5971
recordtype	eprints
spelling	iium-59712012-01-31T06:56:37Z http://irep.iium.edu.my/5971/ Hardware prototyping of an efficient encryption engine Ibrahimy, Muhammad Ibn Reaz, Mamun Bin Ibne Asaduzzaman, Md. Chowdhury, Md. Sazzad Hossien TK7885 Computer engineering An approach to develop the FPGA of a flexible key RSA encryption engine that can be used as a standard device in the secured communication system is presented. The VHDL modeling of this RSA encryption engine has the unique characteristics of supporting multiple key sizes, thus can easily be fit into the systems that require different levels of security. A simple nested loop addition and subtraction have been used in order to implement the RSA operation. This has made the processing time faster and used comparatively smaller amount of space in the FPGA. The hardware design is targeted on Altera STRATIX II device and determined that the flexible key RSA encryption engine can be best suited in the device named EP2S30F484C3. The RSA encryption implementation has made use of 13,779 units of logic elements and achieved a clock frequency of 17.77MHz. It has been verified that this RSA encryption engine can perform 32-bit, 256-bit and 1024-bit encryption operation in less than 41.585us, 531.515us and 790.61us respectively. World Academy of Science Engineering and Technology 2010 Article PeerReviewed application/pdf en http://irep.iium.edu.my/5971/1/Hardware_Prototyping_2010.pdf Ibrahimy, Muhammad Ibn and Reaz, Mamun Bin Ibne and Asaduzzaman, Md. and Chowdhury, Md. Sazzad Hossien (2010) Hardware prototyping of an efficient encryption engine. International Journal of Electrical and Electronics Enginering, 4 (4). pp. 258-264. http://www.waset.org/journals/ijeee/v4/v4-4-33.pdf
repository_type	Digital Repository
institution_category	Local University
institution	International Islamic University Malaysia
building	IIUM Repository
collection	Online Access
language	English
topic	TK7885 Computer engineering
spellingShingle	TK7885 Computer engineering Ibrahimy, Muhammad Ibn Reaz, Mamun Bin Ibne Asaduzzaman, Md. Chowdhury, Md. Sazzad Hossien Hardware prototyping of an efficient encryption engine
description	An approach to develop the FPGA of a flexible key RSA encryption engine that can be used as a standard device in the secured communication system is presented. The VHDL modeling of this RSA encryption engine has the unique characteristics of supporting multiple key sizes, thus can easily be fit into the systems that require different levels of security. A simple nested loop addition and subtraction have been used in order to implement the RSA operation. This has made the processing time faster and used comparatively smaller amount of space in the FPGA. The hardware design is targeted on Altera STRATIX II device and determined that the flexible key RSA encryption engine can be best suited in the device named EP2S30F484C3. The RSA encryption implementation has made use of 13,779 units of logic elements and achieved a clock frequency of 17.77MHz. It has been verified that this RSA encryption engine can perform 32-bit, 256-bit and 1024-bit encryption operation in less than 41.585us, 531.515us and 790.61us respectively.
format	Article
author	Ibrahimy, Muhammad Ibn Reaz, Mamun Bin Ibne Asaduzzaman, Md. Chowdhury, Md. Sazzad Hossien
author_facet	Ibrahimy, Muhammad Ibn Reaz, Mamun Bin Ibne Asaduzzaman, Md. Chowdhury, Md. Sazzad Hossien
author_sort	Ibrahimy, Muhammad Ibn
title	Hardware prototyping of an efficient encryption engine
title_short	Hardware prototyping of an efficient encryption engine
title_full	Hardware prototyping of an efficient encryption engine
title_fullStr	Hardware prototyping of an efficient encryption engine
title_full_unstemmed	Hardware prototyping of an efficient encryption engine
title_sort	hardware prototyping of an efficient encryption engine
publisher	World Academy of Science Engineering and Technology
publishDate	2010
url	http://irep.iium.edu.my/5971/ http://irep.iium.edu.my/5971/ http://irep.iium.edu.my/5971/1/Hardware_Prototyping_2010.pdf
first_indexed	2023-09-18T20:14:48Z
last_indexed	2023-09-18T20:14:48Z
_version_	1777407715972218880

Hardware prototyping of an efficient encryption engine

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