Memristor switching model for digital and analog circuits / Siti Musliha Ajmal Mokhtar
Scaling of complementary-metal-oxide-semiconductor (CMOS) transistor for higher performance device is nearly reaching its limit due to technology limitation issues. In this research, main objective is to incorporate a nanodevice called memristor into CMOS circuit as one alternative to overcome scali...
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| Format: | Thesis |
| Language: | English |
| Published: |
2016
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| Online Access: | http://ir.uitm.edu.my/id/eprint/17788/ http://ir.uitm.edu.my/id/eprint/17788/2/TM_SITI%20MUSLIHA%20AJMAL%20MOKHTAR%20EE%2016_5.pdf |
| Summary: | Scaling of complementary-metal-oxide-semiconductor (CMOS) transistor for higher performance device is nearly reaching its limit due to technology limitation issues. In this research, main objective is to incorporate a nanodevice called memristor into CMOS circuit as one alternative to overcome scaling limitation due to memristor fabrication is compatible with CMOS. The first requirement in this research is to develop SPICE model for memristor in circuit simulation. Research starts with model selection and validation through comparison with fabricated memristor sample followed by model development in LTSPICE. In this research, memristor applications are investigated from both digital and analog memristor resistance switching. For digital, memristor-based logic modules are invested. For analog, a novel design of programmable delay element (PDE) using memristor is proposed. A case study of implementing the proposed PDE in delay locked loop (DLL) is also discussed. For model development, OSM model is validated and has most comparable behavior withb sample. Next, hybrid memristor-based logic gates (AND, NAND, OR, NOR) designs and operation results are discussed. They showed similar operation with CMOS logic. Hybrid XOR shows 88% less area consumption compared to fully CMOS XOR thus supports the main objective. However, hybrid logics have dynamic behavior at output caused by slow memristor switching speed. Speed can be increased through thinner thin film and higher voltage supply. Finally, the proposed PDE showed delays that are programmed by adjusting memristor resistance. Case study of DLL proved proposed
design functionality in more complex system. However, it consumes more area than CMOS DLL. |
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