Optimal nano dimensional channel of GaAs-FinFET transistor

Optimal nano dimensional channel of GaAs-FinFET transistor

This paper investigates the optimal nano-dimensions channel for Gallium Arsenide Fin Field Effect Transistor (GaAs-FinFET) based on I ON /I OFF ratio and subthreshold swing (SS). The impact of reducing channel dimensions (length, width, and oxide thickness) on GaAs-FinFET performance has been evalua...

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Main Authors: Ahmed, Mahmood, Waheb Abdul Jabbar, Shaif Abdullah, Wasan Kadhim, Saad, Hadi, Manap
Format: Conference or Workshop Item
Language:English
English
Published: IEEE 2018
Subjects:
QA75 Electronic computers. Computer science
T Technology (General)
Online Access:http://umpir.ump.edu.my/id/eprint/25345/
http://umpir.ump.edu.my/id/eprint/25345/
http://umpir.ump.edu.my/id/eprint/25345/1/57.1%20Optimal%20nano%20dimensional%20channel%20of%20GaAs-FinFET%20transistor.pdf
http://umpir.ump.edu.my/id/eprint/25345/2/57.%20Optimal%20nano%20dimensional%20channel%20of%20GaAs-FinFET%20transistor.pdf
id ump-25345
recordtype eprints
spelling ump-253452019-11-12T03:01:16Z http://umpir.ump.edu.my/id/eprint/25345/ Optimal nano dimensional channel of GaAs-FinFET transistor Ahmed, Mahmood Waheb Abdul Jabbar, Shaif Abdullah Wasan Kadhim, Saad Hadi, Manap QA75 Electronic computers. Computer science T Technology (General) This paper investigates the optimal nano-dimensions channel for Gallium Arsenide Fin Field Effect Transistor (GaAs-FinFET) based on I ON /I OFF ratio and subthreshold swing (SS). The impact of reducing channel dimensions (length, width, and oxide thickness) on GaAs-FinFET performance has been evaluated in terms of various electrical characteristics (I ON /I OFF , SS, VT and DIBL). The MuGFET simulation tool is used in this study to simulate the current-voltage characteristics for different dimensions of channel. According to highest I ON /I OFF ratio, and nearest SS to the ideal SS, the best channel dimensions of GaAs-FinFET are designed. The results show that the best performance can be achieved with the lowest scaling factor, K of 0.25, when the length is 40 nm, the width is 3 nm, and the oxide thickness is 1 nm. IEEE 2018 Conference or Workshop Item PeerReviewed pdf en http://umpir.ump.edu.my/id/eprint/25345/1/57.1%20Optimal%20nano%20dimensional%20channel%20of%20GaAs-FinFET%20transistor.pdf pdf en http://umpir.ump.edu.my/id/eprint/25345/2/57.%20Optimal%20nano%20dimensional%20channel%20of%20GaAs-FinFET%20transistor.pdf Ahmed, Mahmood and Waheb Abdul Jabbar, Shaif Abdullah and Wasan Kadhim, Saad and Hadi, Manap (2018) Optimal nano dimensional channel of GaAs-FinFET transistor. In: 2018 IEEE 16th Student Conference On Research And Development (Scored), Bangi, Malaysia (26-28 Nov 2018), 26 - 28 Nov 2018 , Bangi Resort, Bangi, Selangor, Malaysia. pp. 1-5.. ISBN 978-153869175-5 https://doi.org/10.1109/SCORED.2018.8710811
repository_type Digital Repository
institution_category Local University
institution Universiti Malaysia Pahang
building UMP Institutional Repository
collection Online Access
language English
English
topic QA75 Electronic computers. Computer science
T Technology (General)
spellingShingle QA75 Electronic computers. Computer science
T Technology (General)
Ahmed, Mahmood
Waheb Abdul Jabbar, Shaif Abdullah
Wasan Kadhim, Saad
Hadi, Manap
Optimal nano dimensional channel of GaAs-FinFET transistor
description This paper investigates the optimal nano-dimensions channel for Gallium Arsenide Fin Field Effect Transistor (GaAs-FinFET) based on I ON /I OFF ratio and subthreshold swing (SS). The impact of reducing channel dimensions (length, width, and oxide thickness) on GaAs-FinFET performance has been evaluated in terms of various electrical characteristics (I ON /I OFF , SS, VT and DIBL). The MuGFET simulation tool is used in this study to simulate the current-voltage characteristics for different dimensions of channel. According to highest I ON /I OFF ratio, and nearest SS to the ideal SS, the best channel dimensions of GaAs-FinFET are designed. The results show that the best performance can be achieved with the lowest scaling factor, K of 0.25, when the length is 40 nm, the width is 3 nm, and the oxide thickness is 1 nm.
format Conference or Workshop Item
author Ahmed, Mahmood
Waheb Abdul Jabbar, Shaif Abdullah
Wasan Kadhim, Saad
Hadi, Manap
author_facet Ahmed, Mahmood
Waheb Abdul Jabbar, Shaif Abdullah
Wasan Kadhim, Saad
Hadi, Manap
author_sort Ahmed, Mahmood
title Optimal nano dimensional channel of GaAs-FinFET transistor
title_short Optimal nano dimensional channel of GaAs-FinFET transistor
title_full Optimal nano dimensional channel of GaAs-FinFET transistor
title_fullStr Optimal nano dimensional channel of GaAs-FinFET transistor
title_full_unstemmed Optimal nano dimensional channel of GaAs-FinFET transistor
title_sort optimal nano dimensional channel of gaas-finfet transistor
publisher IEEE
publishDate 2018
url http://umpir.ump.edu.my/id/eprint/25345/
http://umpir.ump.edu.my/id/eprint/25345/
http://umpir.ump.edu.my/id/eprint/25345/1/57.1%20Optimal%20nano%20dimensional%20channel%20of%20GaAs-FinFET%20transistor.pdf
http://umpir.ump.edu.my/id/eprint/25345/2/57.%20Optimal%20nano%20dimensional%20channel%20of%20GaAs-FinFET%20transistor.pdf
first_indexed 2023-09-18T22:38:52Z
last_indexed 2023-09-18T22:38:52Z
_version_ 1777416779356700672

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