Design consideration for successful delay fault testing in SOC
Delay Fault Testing using scan patterns has been increasingly popular in the DFT world. There’s a debate whether at-speed test with scan patterns can actually replace functional at-speed tests. This paper looks at some of the design considerations for making SoC more delay test friendly and re...
| Main Authors: | , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
ICECE Publications
2004
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| Subjects: | |
| Online Access: | http://irep.iium.edu.my/50147/ http://irep.iium.edu.my/50147/ http://irep.iium.edu.my/50147/4/50147.pdf |