Design consideration for successful delay fault testing in SOC
Delay Fault Testing using scan patterns has been increasingly popular in the DFT world. There’s a debate whether at-speed test with scan patterns can actually replace functional at-speed tests. This paper looks at some of the design considerations for making SoC more delay test friendly and re...
| Main Authors: | , |
|---|---|
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
ICECE Publications
2004
|
| Subjects: | |
| Online Access: | http://irep.iium.edu.my/50147/ http://irep.iium.edu.my/50147/ http://irep.iium.edu.my/50147/4/50147.pdf |
| Summary: | Delay Fault Testing using scan patterns has been
increasingly popular in the DFT world. There’s a
debate whether at-speed test with scan patterns
can actually replace functional at-speed tests. This
paper looks at some of the design considerations
for making SoC more delay test friendly and
ready. The test chip was designed scan ready but
with no delay fault testing constructs. |
|---|