Design consideration for successful delay fault testing in SOC
Delay Fault Testing using scan patterns has been increasingly popular in the DFT world. There’s a debate whether at-speed test with scan patterns can actually replace functional at-speed tests. This paper looks at some of the design considerations for making SoC more delay test friendly and re...
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ICECE Publications
2004
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| Online Access: | http://irep.iium.edu.my/50147/ http://irep.iium.edu.my/50147/ http://irep.iium.edu.my/50147/4/50147.pdf |
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iium-501472016-06-02T02:07:26Z http://irep.iium.edu.my/50147/ Design consideration for successful delay fault testing in SOC Dass, Sreedharan Baskara Hassan Abdalla Hashim, Aisha TK Electrical engineering. Electronics Nuclear engineering Delay Fault Testing using scan patterns has been increasingly popular in the DFT world. There’s a debate whether at-speed test with scan patterns can actually replace functional at-speed tests. This paper looks at some of the design considerations for making SoC more delay test friendly and ready. The test chip was designed scan ready but with no delay fault testing constructs. ICECE Publications 2004-12 Conference or Workshop Item PeerReviewed application/pdf en http://irep.iium.edu.my/50147/4/50147.pdf Dass, Sreedharan Baskara and Hassan Abdalla Hashim, Aisha (2004) Design consideration for successful delay fault testing in SOC. In: 3rd International Conference on Electrical & Computer Engineering ICECE 2004, 28th-30th December 2004, Dhaka, Bangladesh. http://www.buet.ac.bd/icece/pub2004/P015.pdf |
| repository_type |
Digital Repository |
| institution_category |
Local University |
| institution |
International Islamic University Malaysia |
| building |
IIUM Repository |
| collection |
Online Access |
| language |
English |
| topic |
TK Electrical engineering. Electronics Nuclear engineering |
| spellingShingle |
TK Electrical engineering. Electronics Nuclear engineering Dass, Sreedharan Baskara Hassan Abdalla Hashim, Aisha Design consideration for successful delay fault testing in SOC |
| description |
Delay Fault Testing using scan patterns has been
increasingly popular in the DFT world. There’s a
debate whether at-speed test with scan patterns
can actually replace functional at-speed tests. This
paper looks at some of the design considerations
for making SoC more delay test friendly and
ready. The test chip was designed scan ready but
with no delay fault testing constructs. |
| format |
Conference or Workshop Item |
| author |
Dass, Sreedharan Baskara Hassan Abdalla Hashim, Aisha |
| author_facet |
Dass, Sreedharan Baskara Hassan Abdalla Hashim, Aisha |
| author_sort |
Dass, Sreedharan Baskara |
| title |
Design consideration for successful delay fault testing in SOC |
| title_short |
Design consideration for successful delay fault testing in SOC |
| title_full |
Design consideration for successful delay fault testing in SOC |
| title_fullStr |
Design consideration for successful delay fault testing in SOC |
| title_full_unstemmed |
Design consideration for successful delay fault testing in SOC |
| title_sort |
design consideration for successful delay fault testing in soc |
| publisher |
ICECE Publications |
| publishDate |
2004 |
| url |
http://irep.iium.edu.my/50147/ http://irep.iium.edu.my/50147/ http://irep.iium.edu.my/50147/4/50147.pdf |
| first_indexed |
2023-09-18T21:10:51Z |
| last_indexed |
2023-09-18T21:10:51Z |
| _version_ |
1777411242474864640 |