Negative bias temperature instability characterization and lifetime evaluations of submicron pMOSFET

A major effect of different measurement delay in seconds is revealed through quasi DC Stress Measure Stress experiments. We found that different delay of measurements in seconds contributed to different stress time needed to achieve target 10% degradation of Vth. The longer delay, the more time...

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Main Authors: Hatta, Sharifah Wan M., Hussin, Hanim Yati, Soon, F.Y., Abdul Wahab, Yasmin, Abdul Hadi, Dayanasari, Soin, Norhayati, Alam, A. H.M.Zahirul, Nordin, Anis Nurashikin
Format: Conference or Workshop Item
Language:English
English
Published: IEEE 2017
Subjects:
Online Access:http://irep.iium.edu.my/62886/
http://irep.iium.edu.my/62886/
http://irep.iium.edu.my/62886/
http://irep.iium.edu.my/62886/1/62886%20Negative%20Bias%20Temperature%20Instability%20Characterization.pdf
http://irep.iium.edu.my/62886/2/62886%20Negative%20Bias%20Temperature%20Instability%20SCOPUS.pdf
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spelling iium-628862018-06-26T03:55:23Z http://irep.iium.edu.my/62886/ Negative bias temperature instability characterization and lifetime evaluations of submicron pMOSFET Hatta, Sharifah Wan M. Hussin, Hanim Yati Soon, F.Y. Abdul Wahab, Yasmin Abdul Hadi, Dayanasari Soin, Norhayati Alam, A. H.M.Zahirul Nordin, Anis Nurashikin T Technology (General) A major effect of different measurement delay in seconds is revealed through quasi DC Stress Measure Stress experiments. We found that different delay of measurements in seconds contributed to different stress time needed to achieve target 10% degradation of Vth. The longer delay, the more time needed for the device to achieve 10% degradation of Vth. The effect on NBTI degradation is shown to be reliant on stress conditions (stress voltage, temperature) and device architecture (gate dimensions, gate oxide thickness). The NBTI lifetime was predicted by extrapolating lifetime to the nominal operating voltage from Time-to-Fail versus stress bias and oxide electric field plots. Both plots show that the lifetime of degradation parameter of Vth is lower compared to the lifetime of degradation parameter of Idsat. IEEE 2017-10-19 Conference or Workshop Item PeerReviewed application/pdf en http://irep.iium.edu.my/62886/1/62886%20Negative%20Bias%20Temperature%20Instability%20Characterization.pdf application/pdf en http://irep.iium.edu.my/62886/2/62886%20Negative%20Bias%20Temperature%20Instability%20SCOPUS.pdf Hatta, Sharifah Wan M. and Hussin, Hanim Yati and Soon, F.Y. and Abdul Wahab, Yasmin and Abdul Hadi, Dayanasari and Soin, Norhayati and Alam, A. H.M.Zahirul and Nordin, Anis Nurashikin (2017) Negative bias temperature instability characterization and lifetime evaluations of submicron pMOSFET. In: 2017 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE 2017), 24th-25th April 2017, Pulau Langkawi, Kedah. http://ieeexplore.ieee.org/document/8074978/ 10.1109/ISCAIE.2017.8074978
repository_type Digital Repository
institution_category Local University
institution International Islamic University Malaysia
building IIUM Repository
collection Online Access
language English
English
topic T Technology (General)
spellingShingle T Technology (General)
Hatta, Sharifah Wan M.
Hussin, Hanim Yati
Soon, F.Y.
Abdul Wahab, Yasmin
Abdul Hadi, Dayanasari
Soin, Norhayati
Alam, A. H.M.Zahirul
Nordin, Anis Nurashikin
Negative bias temperature instability characterization and lifetime evaluations of submicron pMOSFET
description A major effect of different measurement delay in seconds is revealed through quasi DC Stress Measure Stress experiments. We found that different delay of measurements in seconds contributed to different stress time needed to achieve target 10% degradation of Vth. The longer delay, the more time needed for the device to achieve 10% degradation of Vth. The effect on NBTI degradation is shown to be reliant on stress conditions (stress voltage, temperature) and device architecture (gate dimensions, gate oxide thickness). The NBTI lifetime was predicted by extrapolating lifetime to the nominal operating voltage from Time-to-Fail versus stress bias and oxide electric field plots. Both plots show that the lifetime of degradation parameter of Vth is lower compared to the lifetime of degradation parameter of Idsat.
format Conference or Workshop Item
author Hatta, Sharifah Wan M.
Hussin, Hanim Yati
Soon, F.Y.
Abdul Wahab, Yasmin
Abdul Hadi, Dayanasari
Soin, Norhayati
Alam, A. H.M.Zahirul
Nordin, Anis Nurashikin
author_facet Hatta, Sharifah Wan M.
Hussin, Hanim Yati
Soon, F.Y.
Abdul Wahab, Yasmin
Abdul Hadi, Dayanasari
Soin, Norhayati
Alam, A. H.M.Zahirul
Nordin, Anis Nurashikin
author_sort Hatta, Sharifah Wan M.
title Negative bias temperature instability characterization and lifetime evaluations of submicron pMOSFET
title_short Negative bias temperature instability characterization and lifetime evaluations of submicron pMOSFET
title_full Negative bias temperature instability characterization and lifetime evaluations of submicron pMOSFET
title_fullStr Negative bias temperature instability characterization and lifetime evaluations of submicron pMOSFET
title_full_unstemmed Negative bias temperature instability characterization and lifetime evaluations of submicron pMOSFET
title_sort negative bias temperature instability characterization and lifetime evaluations of submicron pmosfet
publisher IEEE
publishDate 2017
url http://irep.iium.edu.my/62886/
http://irep.iium.edu.my/62886/
http://irep.iium.edu.my/62886/
http://irep.iium.edu.my/62886/1/62886%20Negative%20Bias%20Temperature%20Instability%20Characterization.pdf
http://irep.iium.edu.my/62886/2/62886%20Negative%20Bias%20Temperature%20Instability%20SCOPUS.pdf
first_indexed 2023-09-18T21:29:06Z
last_indexed 2023-09-18T21:29:06Z
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